Application Scheme of Image Acquisition System Based on FPGA Device EP2C5F256C6 Chip


In low-speed data acquisition systems, microcontrollers or DSPs are often used for control; but for high-speed data acquisition occasions such as image acquisition, this solution cannot meet the needs. Therefore, this solution greatly wastes the port resources of the microcontroller or DSP, and has poor flexibility; if the serial port method is used to collect data, on the one hand, the data acquisition speed will be reduced, and on the other hand, the CPU resources will be greatly consumed. The system adopts FPGA as the main control unit of data acquisition, and all control logic is completed by hardware, which has fast speed, low cost and strong flexibility. In order to increase the buffer function, the system expands the 256Mb RAM outside the FPGA, which not only increases the buffer capacity, but also greatly reduces the read and write frequency, effectively reducing the burden on the host computer CPU. Among the image data interfaces, VGA and PCI-Express are more common. These interfaces have poor scalability and high cost. The system adopts high-speed USB interface as the communication interface with the host computer, which is fast, easy to install and flexible.

1 System block diagram

The system block diagram is shown in Figure 1. The FPGA control unit adopts Cyclone II series of EP2C5F256C6A1tera, which is mainly composed of 4 parts - main control module, CMOS sensor interface, RAM controller and EZ-USB interface controller. The Sensor interface is responsible for completing the SCCB timing control, the RAM controller is used to implement the timing of RAM read, write and refresh operations, the USB interface module completes the data read and write between the main control module and the EZ-USB; and the main control module is responsible for the slave EZ-USB. The host computer command received by the USB part is analyzed, and the corresponding signal is generated after the command is analyzed to control each corresponding module, such as the image format transmitted by the CMOS sensor, the read and write mode of the RAM, and the burst length.

2 OV7620 module design

The image sensor adopts OV7620, and the interface diagram is shown in Figure 2. The sensor is powerful and provides a variety of data format output, automatic white noise removal, white balance, color saturation, hue control, window size, etc. can be set through the internal SCCB control line. The OV7620 is a CMOS color image sensor. Support continuous and interlaced scanning, VGA and QVGA two image formats; maximum pixel 664×492, frame rate 30fps; data formats include YUV, YCrCb and RGB. 0V7620 supports SCCB setting mode and auto-loading default setting mode, the selection is controlled by SCCB. This system only needs to support the SCCB mode, and the SBB is grounded during design. After power-on, the FP-GA sets the OV7620 through the SCCB bus, and the system can also accept commands from the host computer to set its working mode. The SCCB bus timing is similar to the I2C bus timing, SIO-0 is equivalent to SDA, and SIO-1 is equivalent to SCL. OV7620 works in slave mode. In the process of writing the register, first send the ID address of the OV7620, then send the destination register address of the written data, and finally send the data to be written.

3 RAM timing control module

The RAM controller interface is mainly used to realize the basic operation timing of RAM, such as charging (refreshing) timing, mode setting timing, reading and writing timing, etc. The read and write commands are issued by the main control module and executed by the main control module. controller. The system adopts Hynix's HY57V561620F(L)T(P), which can realize large-capacity data storage of 256Mb.

The sequential controller is implemented by a finite state machine (FSM), and its state transition diagram is shown in Figure 3. 200μs after power-on reset, all RAM blocks are precharged. The pin level of the charging operation is shown in Table 1. After charging is completed, all blocks are refreshed through tRP, and the mode setting state is entered after a delay of tRFC. In the mode setting state, it is necessary to set the RAS delay, burst length, etc., enter the idle state after a delay of tMRD, and wait for the read and write commands from the main control unit. In idle state, all rows in RAM need to be refreshed every 64ms. In this design, the timing refresh module is designed as a counter, and the counting pulse is selected from the clock of the controller itself. Since RAM requires a maximum time interval between refreshes of no more than 64 ms, assuming a system clock frequency of 100 MHz, a clock period of about 0.01 μs, and all 8 192 rows must be refreshed within 64 ms, the maximum count should be 781 times (64 ms/8192/0.01 μs). The system uses 700 count pulses to generate refresh requests.

4 EZ—USB transfer controller

CY7C68013 is the EZ-USB FX2 series chip of Cypress Company, and the pin connection diagram is shown in Figure 5. This series of chips integrates USB2.O transceiver, serial interface engine (SIE), on-chip 8.5KB enhanced 8501 RAM, 16 KB RAM, 4 KB FIFO memory, I/O ports, data bus, address bus and general-purpose Programming Interface (GPIF); There are 3 interface modes - Port Mode, Slave FIFO Interface Mode and GPIF Interface Mode. In port mode, all I/O pins can be used as 805l general purpose I/O ports. As the most basic data transmission method, the data transmission is mainly completed by the firmware program and requires the participation of the CPU, so the data transmission rate is relatively low. In slave FIFO interface mode, external logic or an external processor can be connected directly to the FX2 endpoint FIFO. The GPIF interface mode uses PORTB and PORTD to form a 16-bit data interface to the four FX2 endpoints FIF0 (EP2, EP4, EP6 and EP8). The GPIF is directly connected to the FIFO as an internal main controller, and generates user-programmable control signals to communicate with the external interface. The data transmission of the latter two modes is completed by executing the USB protocol by itself, and the microprocessor does not participate in the data transmission, thereby greatly improving the data transmission rate.

in conclusion

Through the above design, the bottleneck of high-speed data sampling and transmission is well resolved, and the collection of high-speed image data is truly realized with short delay. Due to its low cost and easy installation, it has broad market prospects and can be used in fields such as teleconferencing, telemedicine, and distance education that require high-definition image transmission. The innovation of this design is to adapt to the application requirements of different image data, and realize a variety of speed reading and writing modes, which can be real-time burst length reading and writing and high-speed full-page reading and writing.